工作地:
新竹縣竹北市
工作內容:Job Responsibilities
• Work closely with circuit designers to complete the physical layout and its verification across different country.
‒ Receive a schematic from an Analog IC Designer and use a CAD tool to graphically design the layers of that schematic.
‒ Use problem solving & strong communication skills, , experience, and creativity to layout circuits that meet size, schedule, and performance specifications.
• Run physical design verification tools to debug, improve, and verify layout blocks.
Job Requirement
• Bachelor’s degree in Computer Science, Electrical Engineering or related fields with 3~5 years layout experience.
‒ Including at 1~2 years in FINFET process node. 5nm/3nm is preferable.
• Or 5+ years experience in IC layout design, especially ≥2 years in FINFET process node. 5nm/3nm is preferable.
• Full-custom circuit layout/verification. Experience in one or more of the following area is preferable.
‒ Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.
• Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS, etc).
‒ Proficient at debugging/fixing LVS/DRC errors.
• Experience with EMIR analysis, ESD, antenna and related layout solutions.
• Must have strong communication skills and be a team player.
• Ability to work independently & Collaborate with team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.
• Each project can last from a couple months to a year and a half.
• You will likely work on just one project in that time, but may be asked to switch to something else if priorities change. Your flexibility is appreciated.
• Fluent in English is a plus.