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R&D Power Grid Design and Sign-Off Engineer
面試心得
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企業名
台灣積體電路製造股份有限公司(台積電)
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工作地點
新竹市新竹市
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薪資
面議(經常性薪資達4萬元或以上)40000~0元
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工作內容
【本職缺僅接受台積電官方網站投遞】
請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:
https://careers.tsmc.com/careers/JobDetail?jobId=475&source=1111
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.
Organization Introduction:
We are power grid design and sign-off team for digital design inside TSMC. The mission is to develop power grid design and co-optimize with semiconductor process in advanced technology nodes for most updated commercial design contents (CPU, GPU, SoC, etc.)
Our power grid designs are references for worldwide 1st Tier design houses.
Responsibilities:
1. Develop power grid structure for most updated commercial design contents (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance.
2. Provide design solutions for IR/EM and routing optimization.
3. Co-work with process R&D for process tuning to achieve better PDN (Power Delivery Network) design.
4. Support TSMC advanced process node test chip PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out.
5. Provide guidance and suggestion to PnR (Place and Route) designer on PDN issue fixing.
台灣積體電路製造股份有限公司(台積電)-使用1111轉職專區
https://central1111.com.tw/turn/