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A10/A14 RD Integration Engineer
面試心得
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企業名
台灣積體電路製造股份有限公司(台積電)
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工作地點
新竹市新竹市
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薪資
面議(經常性薪資達4萬元或以上)40000~0元
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工作內容
【本職缺僅接受台積電官方網站投遞】
請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:
https://careers.tsmc.com/careers/JobDetail?jobId=353&source=1111
Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.
RD Integration starts with the definitions, including transistor architecture and design building blocks, of a new technology node. Then, a manufacturable process flow is developed for evaluations and further improvements. The tasks may involve multidiscipline technical knowledge bases and project management skills. The job will require a lot of collaborations, so frequent communication should be expected. Test structure are designed in order to evaluate the manufacturing processes. Test vehicles will be built, and real chips will be validated through yield, performance, and reliability learning cycles. The goal is to deliver an optimized semiconductor technology that will meet the required chip performance, power, area-per-function, costs, and time-to-market (PPACt) for our customers.
Responsibilities:
1. Development of world-class cutting-edge technology, and responsible for the success of the A10/A14 technology:
(1) Process integration across process modules, including test key design, tape out, device analysis,
simulation, model, and robust.
(2) Test key designs for design rule validation, electrical modeling, and yield learning.
(3) Characterization of state-of-the-art devices, spice targets‘ setting for modelling, occasional bench
measurement.
(4) Lot handling: periodically serves as on-duty engineer to coordinate device lots‘ handling.
2. Advanced process integration development: integration and baseline sustaining to meet process KPIs on performance/ yield/ reliability/ manufacturability in A10/A14 program.
3. Advanced integration baseline process transfer to volume production.
4. Data analysis to identify the issue and issue owner.
5. Co-work with various teams to evaluate new processes and solve the issue.
6. Routine integration logistic job.
台灣積體電路製造股份有限公司(台積電)-使用1111轉職專區
https://central1111.com.tw/turn/