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ASIC Implementation Engineer
面試心得
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企業名
聯發科技股份有限公司
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工作地點
新竹市東區
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薪資
面議(經常性薪資達4萬元或以上)0~0元
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工作內容
- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power.
- Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures.
- DFT insertion, ATPG and gate-level simulation
- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
- Interact with Physical Design Engineers and provide them with timing/congestion feedback.
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