新竹市東區轉職工作機會，轉職跳槽推薦工作，提供履歷健診等強化服務|1111轉職專區-第50頁

＜Data center＞Serdes系統架構研發工程師面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1. 高速Serdes系統技術開發(200Gbps+), 包括電通訊與光通訊(optical interconnect) 2. 定義系統技術規格並與設計團隊(Analog, Digital, Algorithm)討論系統架構, 建立模型模擬評估 3. Serdes 關鍵技術評估與開發( e.g., Next Gen Serdes, optical nonlinearity compensation, CPO technology) 4. 協助Serdes IP驗證問題分析

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＜Data center＞SerDes 資深韌體設計驗證工程師面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1. 應用於I/O 小晶片的 SerDes 設計驗證工作. 包含從原型測試到量產晶片, 並與類比, 數位和演算法設計團隊合作. 2. 負責實現 SerDes 韌體設計, 以驗證連線效能和實現量產測試 3. 負責建立自動測試和資料分析, 以測試SerDes的晶片特性和分析失效晶片

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工作適配度－%

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＜Data center＞Senior Signal and Power Integrity Engineer 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

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工作適配度－%

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＜Data center＞Senior Power Integrity Engineer_HsinChu/Taipei 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞Senior Photonics IC Design Engineer 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 • Design, simulate and test various building blocks for photonic ICs such as modulators, filters, and detectors. • Develop mathematical models of photonic components for co-simulation with electronic circuits. • Contribute to the integration and testing of Photonic & Electronic ICs, collaborate with cross functional teams to improve system performance and optimize designs. • Must be proficient in programming (e.g. Python or MATLAB) for design automation

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞Senior Manufacturing and Test Engineer 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 The Senior Manufacturing and Test Engineer is responsible for improving manufacturing and test flows to optimize quality, yield and power in AI ASICs. Activities include DFT definition, coverage analysis and test content improvements at socket & system level to drive yield and quality. Collaboration across design and manufacturing teams to correlate pre-silicon to post-silicon through data analysis, building quality models and driving optimizations is expected. Deep understanding and experience in DFT architecture, quality, yield and power measurement flows is needed.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞Power related PCB Design Engineer 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1.PCB power related hardware design：Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 2. System specification and design requirement collection. 3. System hardware verification and testing: function verification and power quality measurement. 4. Cross-organizational collaboration: Collaborate with IC design team, system team, SI/PI team, layout team, etc. to complete system design, production and verification. 5. Customer and related manufacturer support: including technical document writing, customer reference design support, on site support, etc.

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應徵

工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞Playbook Program Manager 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1. Develop Playbook for ASIC design 2. Monitor the project execution based on the Playbook 3. Coordinate among different teams to improve Playbook

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應徵

工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞On-die IR integrator 面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1. 整合IR 資訊和內部團隊合作解決 IR 問題 2. 產生並分析 power 資訊 3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題

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應徵

工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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＜Data center＞IC低功耗工程師/架構師面試心得
企業名聯發科技股份有限公司
工作地點新竹市東區
薪資面議（經常性薪資達4萬元或以上）40000~40000元
工作內容 1. 數位晶片設計流程與整合 2. 熟悉低功耗的設計流程(和架構)

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應徵

工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

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