新竹縣轉職工作機會，轉職跳槽推薦工作，提供履歷健診等強化服務|1111轉職專區-第457頁

研發專案經理
企業名先進材股份有限公司
工作地點新竹縣竹北市
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容 1. 驗證計劃提案(客戶需求、項目目標、時間表等相符) 2. 成本分析 3. 製造設備評估及提案 4. 產品商品化 5. 專案時程規劃及控管 6. 開發流程標準化控管 7. 專案風險管控 8. 跨部門溝通協調 9. 客戶需求定義 10. 其他主管交辦事項

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7/17

全科班老師
企業名私立天籟文理短期補習班(徐薇英文松林分校)
工作地點新竹縣新豐鄉
薪資月薪35000~40000元
工作內容 1. 進行跨領域科目教學，設計課程內容並講授重點知識。 2. 規劃並執行教學活動，確保學生理解教學目標。 3. 編寫並設計課程教材及補充講義，提升學習效果。 4. 分析學生學習進度，提供個別化輔導建議。 5. 主動提供親師溝通，分享學員學習狀況和成果。 6. 協助舉辦補習班活動，增強課外學習興趣。 7. 配合團隊完成行政支援與班級管理工作。 8. 定期進行成果評估，制定改善計劃以提升學習能力。

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Materials Management Engineer (MM) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪35000~40000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16580&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: Opening roles for you: 1. Global Procurement and Supply Planning Professionals 2. Global Logistics Digital Transformation Engineer 3. Responsible Supply Chain Management Engineer 4. Supply Chain Auditor 5. Resource Recovery Management Engineer For detailed job description, please refer to: https://careers.tsmc.com/careers/JobDetail?jobId=16580&source=1111&tags=AO+2026_1111

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

美語老師(兼職皆可)
企業名私立天籟文理短期補習班(徐薇英文松林分校)
工作地點新竹縣新豐鄉
薪資論件計酬600~0元
工作內容 1.語言教學 2.設計相關課程及開發課程 3.上課講義編寫 4.配合補習班活動 5.學員成果評估

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Corporate Planning Organization (CPO) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16579&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Our key responsibilities include: 1. We ensure customers‘ demands are well satisfied in the rapid market, win customer trust, enhance operation efficiency and reach profit maximization. 2. We drive for business effectiveness to bring world changing innovation into reality. 3. Our resources, production and demand planning, pricing, and system integration team develop flexible planning and provide quick responsiveness to coordinate needs between factories and customers. 4. We seek individuals who meet the following criteria: (1) Possess experience in Business, Industrial Engineering, Computer Science, Information Systems, Information Science, or Semiconductor Industry. (2) Have skills in logic thinking and communication, learning agility, and business acumen. Opening roles for you: 1. Account PC Planner 2. Fab Production Control Planner 3. Fab Rationalization Engineer 4. Operation Resources Planning Engineer 5. DevOps Engineer 6. ML/AI Engineer 7. Corporate Planning Associate For detailed job description, please refer to: https://careers.tsmc.com/careers/JobDetail?jobId=16579&source=1111&tags=AO+2026_1111

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

2026 台積電預辦登積計畫 TSMC Qualification for AO(預聘) / RDSS(研發替代役) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16564&source=1111&tags=AO+2026_1111 因為期待無限可能，所以選擇台積電！台積公司致力於營造一個充滿挑戰、持續學習且充滿樂趣的工作環境，並提供高於業界平均水準的薪酬與福利。加入台積電，您將有機會與世界一流的卓越夥伴共事，透過最先進的製程技術，共同成就改變世界的偉大事業。每一項突破與創新，都凝聚了我們的努力與心血。 2026年台積電預辦登積計畫：招募2026年應屆畢業生與研發替代役台積電誠摯邀請「志同道合」的您，透過「線上應徵」事先註冊履歷。符合資格者將享有優先面試的機會！參與2026年預聘暨研發替代役熱門職缺，您將可： ▪ 畢業前即拿到聘書 ▪ 與優秀產業菁英共事 ▪ 在國際舞台盡情發揮截止收件日：2025/10/31 如您對此計畫感興趣，台積電將前往校園辦理實體行動徵才車活動；活動當天不僅請您喝咖啡，並安排畢業校友與同學們互動交流，機會難得敬請把握機會。校園場次與報名資訊請參考官網（如未報名成功，也歡迎至現場和台積人資互動，現場投遞履歷，還可抽《限量》積星神秘小禮！）此外，我們為同學準備了四場次不同語系線上說明會(9/19中文、10/3日文、10/8中文、10/22英文)，歡迎報名參加，以掌握台積電的趨勢、組織概況與求職撇步！報名連結清參考官網（採線上報名，報名成功後將由台積電招募團隊審核，並透過系統自動發送e-mail通知，可重複報名不同場次聆聽）建議您根據學習領域與專業，投遞申請以下2~4個職位。符合主管需求者，將會收到面談邀請通知。 ▋歡迎志同道合的你，一起加入台積電 ▋世界上的每一個夢，都由我們來圓夢 Because we believe in endless possibilities, we choose TSMC! TSMC offers a wide variety of fulfilling experience and opportunities across our organization in many different locations. By joining TSMC, you will work with the high-performing teams in the industry and achieve your full potential through a comprehensive and systemized learning program here. We are devoted to achieving technology advancement, pursuing manufacturing excellence, and optimizing customer service. 2026 TSMC Advanced Offer and R&D Substitute Service Program Welcome to submit your resume via our application systems and apply to the following vacancies : 2026 TSMC Advanced Offer(AO) and R&D Substitute Service Program (RDSS). You will then be able to: • Get the offer before graduation. • Work with professional experts in the industry. • Fulfill yourself on the world stage. Application Deadline: October 31, 2025 Attending Campus Recruitment events with TSMC to enjoy a coffee with the industry experts to find out what suit you the best. For campus event schedule and registration details, please refer to TSMC career website (even if you are unable to register successfully, feel free to visit our booth and have a chat with us.) Submit your resume now, and gain a chance to win a limited TSMC’s gift! We’re also organizing a series of 〝TSMC Campus Recruitment Online Briefing Session〝, where you can find out more about industry trend, career opportunities, and life at TSMC. The sessions will be held on Sep. 19, Oct. 4, Oct. 8, and Oct. 16 respectively. Registration link: Please refer to the career website *TSMC Talent Acquisition Team will send a confirmation email to the eligible applicants who have successfully registered to the events. We recommend you applying for two to four positions based on your academic background and professional expertise. If your qualifications meet the position requirements, you will receive an invitation for interviews. ▋Join TSMC｜Together, We Grow ! 2026 TSMC AO&RDSS Recruitment Job (Please refer to the job in the career website for the details for each job below): R&D (研究與發展組織) 　1-1 Research and Development Engineer (R&D) 　1-2 Design and Technology Platform Engineer (DTP) 　1-3 Specialty Engineer (Specialty) 　1-4 Integrated Interconnect & Packaging Engineer (IIP) 　1-5 Pathfinding for System Integration Engineer (PSI) Operations (營運組織) 　2-1 Process Integration Engineer (PIE) 　2-2 Process Engineer (PE) 　2-3 Equipment Engineer (EQ) 　2-4 Intelligent Manufacturing Engineer (IMC/MFG) 　2-5 Facility Engineer (FAC) 　2-6 Product Engineer (PE) 　2-7 Advanced Packaging Technology and Service Engineer (APTS) 　2-8 Quality & Reliability Engineer (Q&R) Corporate Business (策略暨支援組織) 　3-1 Information Technology Engineer (IT) 　3-2 Corporate Planning Organization (CPO) 　3-3 Materials Management Engineer (MM) 【履歷填寫重點提醒】 1. 請務必優先填寫完成「畢業學校、畢業年份、就讀科系」後再更新履歷細節資訊，在系統資料送出後，您仍可以在收到面試邀請前持續更新內文。 2. 請詳細填寫履歷資料，包括學歷、專業關鍵字及自傳等內容；若您非外籍人士，除專業關鍵字外，其他欄位請以全中文填寫即可。 3. 自傳與專業關鍵字欄位有字數限制(1000字)，請確認字數是否符合要求，以免導致網頁無法成功送出。 4. 若履歷欄位為下拉式選單，當找不到合適內容時，可點選「其他」手動資料送出。更多2026預聘暨研發替代役招募活動，請密切關注台積電FB粉絲專頁@加入台積共創奇蹟【Notes for Resume Submission】 1. Please prioritize completing the 〝Graduation School, graduation year and major〝 sections when submitting your resume. You can continue to update the content before receiving an interview invitation after the system data has been submitted. 2. Please click “Apply” and provide detailed resume information, including your education level, profession (with keywords that best describe your domain expertise) and autobiography, etc. If you are not a foreigner, please fill out the form (except for the keywords) in Mandarin. 3. Please make sure that the total work counts of your autobiography and keywords (domain description) are within a maximum of 1,000 characters respectively to prevent technical issues. 4. If a resume field is presented as a dropdown menu and you cannot find a suitable option, you may select 〝Other〝 and manually submit the required information. For more information about the 2026 Advanced Offer (AO) and R&D Substitute Service Program (RDSS), please follow our TSMC Facebook fan page@加入台積共創奇蹟

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Research and Development Engineer (R&D) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16565&source=1111&tags=AO+2026_1111 Description : R&D Engineers will be part of a grand joint-force working on advanced technologies, including but not limited to exploratory research in advanced device architecture, market-oriented design IP enablement, device and process integration for manufacturability, package-level interconnect solutions, and novel material/equipment/process evaluations. Responsibilities: 1. Research & Pathfinding (1) New material and new process pathfinding to enable new device architecture with integration. (2) New tool pathfinding for new materials to enable the next nodes. (3) Design, execute and analyze experiments to meet R&D engineering specifications. (4) Process stability & manufacturability improvement for yield and reliability qualification. (5) Process/tool transfer to development R&D or volume manufacturing (Fab). (6) Highly motivated individuals with a strong technical background and teamwork skills. 2. Integration (1) Technology definition: design rules, design-technology co-optimization, logic/memory IP evaluations, etc. (2) Technology development infrastructure: productivity enhancement, product inspection methodology, mask-making, and test flow, etc. (3) New test vehicle establishment and validation: improvement of device yield and reliability (learning cycles). Improve yield and reduce defects by quantifying defect attributes using programming skills and developing effective detection methodologies. (4) Customer design enablement: SPICE Modeling and IP qualifications. 3. Module (1) Develop advanced processes, materials, tools, models, and computational methodologies for leading edge technologies. (2) Deliver manufacturable, stable, cost-effective technologies with device performance improvement for yield and reliability qualification. (3) Transfer process and tool to high volume manufacturing fab. 4. R&D Process Center (1) PE: Advanced module process development and baseline sustaining. (2) EE: Handle advanced equipment at R&D stage. Install, warm up, sustain and troubleshooting solve with new technology equipment. (3) MFG: Oversee the daily operations of IC foundry to ensure that all profiling operations, workflow, and customer reports are consistent with agreed upon service operations.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Design and Technology Platform Engineer (DTP) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16566&source=1111&tags=AO+2026_1111 Description : At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. Responsibilities: 1. Physical Designer The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 2. Standard Cell Engineer (1) Pathfinding of library characterization for leading edge tech nodes. (2) Support industrial standard library kits generation and QC. (3) In-house library generation flow and/or utility development. (4) RC parasitic extraction analysis and APR related analysis. 3. Layout Engineer (1) IC layout for advanced technology (Std. cell/Memory/AMS/IO). (2) Layout structure development for new technology. (3) Pathfinding for new technology development. (4) Customer engagement and layout support. (5) Design and technology co-optimization (DTCO). (6) AI and automation for layout and physical design. 4. System and Chip Design Solutions Development Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 5. FE design & DFT (1) Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG). (2) Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. (3) Technology benchmarking for PPA evaluation of the advanced nodes. (4) DTCO (Design & Technology Co-Optimization) pathfinding and development. 6. SRAM Engineer (1) SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. (2) RRAM/MRAM, emerging memory development. (3) In memory computing research and development. 7. Design Flow/Methodology (1) Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support. (2) Advanced technology design development flow development and technical support. (3) Automation program development to support design kits and flow development productivity/quality.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Specialty Engineer (Specialty) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16567&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1. Novel devices developing for specialty technology. 2. Device Simulation, Test-chip design tape out and measurement system developing. 3. Process flow developing for production. 4. Collaborate with related teams for Design Collaterals (DRM/DRC/LVS/SPICE/PDK) developing.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

【2026 TSMC RDSS & AO】Integrated Interconnect & Packaging Engineer (IIP) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資論件計酬600~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16568&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: As a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer‘s variety applications. 1. Integration (1) Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline. (2) Package level reliability, failure mode analysis and improvement plan. (3) Customer technical interface, new tape out and lot handle. (4) Handover developed technologies to manufacturing groups for production. 2. Module Development (1) Be responsible for CVD/PVD/CMP/Lithography/Etch/Polymer/Bonding/Clean module development for 3DIC projects. (2) New technology, materials survey, and process improvement on 3DIC package structures. (3) Process development and tool transfer to mass-production development. 3. Simulation (1) Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment. (2) Practice FEM and DOE in problem solving and path finding particularly on packaging. (3) Continue improvement in simulation methodology, material modeling and script automation.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

7/17

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