新竹縣寶山鄉轉職工作機會，轉職跳槽推薦工作，提供履歷健診等強化服務|1111轉職專區-第49頁

【2025 Campus Recruitment】Advanced Packaging & Testing Engineer (APTS) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15387&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: TSMC‘s advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc. This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration. TSMC‘s packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution. TSMC‘s advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields. TSMC‘s advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.

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【2025 Campus Recruitment】Product Engineer (PE) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15386&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 加入台積電，成為產品工程師，你將有機會參與世界級先進製程技術，與頂尖團隊合作，挑戰技術極限！你將負責協助產品導入量產、提升良率，並確保產品符合客戶的最高標準。在這裡，你將學習到最先進的半導體技術，並為推動科技發展貢獻力量。我們的專業涵蓋非常廣，從成熟廠到先進廠、從邏輯產品到特殊應用甚至到封裝測試，能夠對產品有全面的了解與完整分析的能力。 1. Leading edge product development. Learn the most advanced technology in semiconductor manufacturing, identify effective process solution for yield and chip performance improvement. 2. Involving cross-team work for joint project development. Coordinate with customer/Fab/different support team closely to address improvement opportunities and work-out the solution. 3. Expanding wider vision with learning device engineering, manufacturing process, yield / WAT analysis, design rule, wafer CP test knowledge, by using comprehensive analysis skills to solve product issue. 4. Developing HV, embedded memory, RF, MEMS, and CIS products falls under the category of 〝More than Moore〝. In this role, you will collaborate with R&D and customers to develop new applications using mature Si process technology.

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工作適配度－%

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5/2

【2025 Campus Recruitment】Facility Engineer (FAC) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15385&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 廠務工程師為整合各項廠區資源，提供晶圓生產所需之電力、水、氣體、化學品、空調等，為台積高度智慧自動的生產單位，供應最高品質、最穩定的生產作業環境。近年廠務工程師更肩負環境保護與永續的責任，如何精進節水、節能、減碳、環保的廠務運轉技術，更是廠務工程師可以發揮專業與創意的主舞台。 1. Responsible for the planning, constructing, operating, and maintaining semiconductor plant facility systems, including risk analysis of facility system operations and supply quality, allocating resources and energy, managing construction safety. 2. Provide a stable facility system, including power, water, gas, chemicals and HVAC, to meet wafer production requirements. 3. Collaborate with other departments to ensure that the facility system is operating at the highest level of quality when on duty. 4. Construction management & project coordination.

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5/2

【2025 Campus Recruitment】Intelligent Manufacturing Engineer (IMC/MFG) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15384&source=1111&tags=domestic+campus+2025_1111 Responsibilities: As a global semiconductor technology leader, TSMC is seeking an Intelligent Manufacturing Engineer to join our team. Our commitment to driving manufacturing excellence has led us to integrate artificial intelligence, machine learning, expert systems, and advanced algorithms to build up an intelligent manufacturing environment. Join TSMC, we are the most advanced technology team and connect with the world, as we head towards an unlimited future. We look forward to you joining us! You will be assigned to one of the following five roles according to your interest, experiences, and technical background. 1. MFG Intelligent Manufacturing Engineer As an Intelligent Manufacturing Engineer, you will be responsible for the development and maintenance of these intelligent manufacturing systems, which are widely used for scheduling and dispatching, employee productivity, equipment productivity, process and equipment control, quality defense, and robotic control. By optimizing quality, productivity, efficiency, and flexibility, you will play a crucial role in driving the success of our manufacturing operations. (1) Smart manufacturing engineers will learn leading artificial intelligence manufacturing technologies worldwide. (2) Big data analysis, improving production efficiency: Through data analysis, identify bottleneck machines and improve machine production efficiency. Breakthrough analysis and dispatching project system, optimize production resources and maximize manufacturing efficiency. (3) Machine learning, creating unlimited possibilities: Utilize cutting-edge machine learning technology to improve the production process and create innovative applications that achieve optimal scheduling and maximize wafer production capacity. 2. CIM Intelligent Manufacturing Engineer (1) Software Developers: Design and develop intelligent manufacturing solutions for factory automation, manufacturing scheduling and dispatching, decision making and engineering analysis. (2) Dispatching Algorithm Developers: Heterogeneous data integration and corresponding solution design and development. (3) Quality Management Engineer: Server maintenance and related setting support including routine upgrades, troubleshooting with AP teams, high-availability architecture, virtual machines solutions, firewall rule, IIS, Nginx, database middle etc. 3. Data Analyst & Data Scientist (1) Application of statistics, machine learning, data mining, pattern recognition and other data analysis by AI techniques. (2) Your main responsibility will be to collect, explore, and extract insights from very large scale structured and unstructured data and explain these insights with the help of data visualization tools to support fab operations. 4. AMHS (Automated Material Handling System) Engineer (1) AMHS (Software) system & AI development/(Hardware) layout design & transport simulation. (2) Enhance System Performance, Quality and Reliability. (3) Coordinate cross-organization AMHS projects. 5. PIDS/WAT (Wafer Acceptance Test) Engineer (1) New WAT tool data matching and release. (2) WAT quality/manufacturing efficiency improvement. (3) WAT tool, recipe, and system management. (4) WAT productivity and quality improvement. (5) WAT tool and systematic issue troubleshooting. 6. PIDS/NTO (New TapeOut) Engineer (1) Handle mask tapeout and manufacturing flow creation. (2) Manage projects related to NTO system development and enhancement. 7. Quality Management Engineer (1) Manage audit, defense, and quality systems. (2) To perform data analysis and simulation.

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5/2

【2025 Campus Recruitment】Equipment Engineer （EQ）面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15383&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 機台是工廠穩定運作的基礎，我們在生產線上，負責高端精密、高單價半導體設備的維護、保養並判斷、解決機台發生的問題；如此可減少機台當機的時間與提升機台可運轉的時間，進而降低生產成本並提升公司的獲利能力。 1. Master Nano Diffusion, Thin Film, Lithography, Etching, or Metrology equipment. 2. Sustain and troubleshoot issues with high-tech equipment. 3. Improve and enhance the efficiency and productivity of equipment. 4. Plan and execute the analysis or defect detection projects. 5. Communicate with cross-functional engineers or vendors.

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5/2

【2025 Campus Recruitment】Process Engineer (PE) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15382&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 我們在第一線負責晶片製造過程，改善機台製程參數的設定，提升良率並讓機台每單位時間產出增加，也降低生產成本；半導體製程可大致分為四大模組，大致流程順序為薄膜沈積、黃光微影製程、溼式與乾式蝕刻、熱製程與離子摻雜(擴散)。 1. To be responsible to drive leading edge process/device/advanced packaging development and optimization of CMOS/Flash/Specialty devices in order to meet scaling, performance, reliability, and manufacturability requirements. 2. Identify and solve IC process and device problems.

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5/2

【2025 Campus Recruitment】Process Integration Engineer (PIE) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15381&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 我們確保晶片的品質、持續提升良率，提供給客戶具有競爭力且高品質的晶片，讓電子產品不但先進且效能穩定；製程整合工程師為半導體製造中的重要協調者，需要與客戶溝通了解客製化的晶片應用需求，再將訊息帶回廠內，與各工程單位合作。良率精進工程師監控晶片的良率與缺陷，使用量測機台監測晶片的缺陷，找出可能的問題，再與製程解決問題。 1. A highly motivated individuals with a strong technical background and capabilities to develop and sustain process technologies for logic, flash memory, and specialty products. 2. Working with a team which may include device, integration, yield, lithography, etch and thin films or external suppliers to drive leading-edge integrated module development, control and improvements. 3. Be responsible for sustaining ownership such as day-to-day operations, equipment troubleshooting and mentoring technicians.

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【2025 Campus Recruitment】Pathfinding for System Integration Engineer (PSI) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15380&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. The Job Role: 1. Highly motivated veteran and new talents to join force research and pathfinding in Advanced packaging and system integration technologies for both extending Moore‘s Law and in post-Moore era. 2. Long prospective career path in semiconductor technologies looking at more Moore‘s and beyond Moore‘s Law Eco-industry. Responsibilities: 1. Integration engineering for process integration and device/system level modeling, including electrical, thermal, and mechanical modeling. 2. Module engineering in advanced FEOL/MEOL/BEOL wafer process modules, and in advanced system packaging, including wafer level fan-out, interposers, and 3D chip stacking. 3. Silicon photonics expertise in the following areas: optical components design (lens, modulator, detector, waveguide w/ various materials), photonic circuits design (w/ focus on optical communication), and computer system architect (w/ focus on parallel processing and high-speed networking).

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5/2

【2025 Campus Recruitment】Integrated Interconnect & Packaging Engineer (IIP) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15379&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: As a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer‘s variety applications. 1. Integration (1) Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline. (2) Package level reliability, failure mode analysis and improvement plan. (3) Customer technical interface, new tape out and lot handle. (4) Handover developed technologies to manufacturing groups for production. 2. Module Development (1) Be responsible for CVD/PVD/CMP/Lithography/Etch/Polymer/Bonding/Clean module development for 3DIC projects. (2) New technology, materials survey, and process improvement on 3DIC package structures. (3) Process development and tool transfer to mass-production development. 3. Simulation (1) Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment. (2) Practice FEM and DOE in problem solving and path finding particularly on packaging. (3) Continue improvement in simulation methodology, material modeling and script automation.

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5/2

【2025 Campus Recruitment】Design and Technology Platform Engineer (DTP) 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資面議（經常性薪資達4萬元或以上）40000~0元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15377&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. Opening roles for you: 1. Physical Designer 2. Standard Cell Engineer 3. Layout Engineer 4. System and Chip Design Solutions Development 5. FE design & DFT 6. SRAM Engineer 7. Design Flow/Methodology For detailed job description, please refer to: https://careers.tsmc.com/careers/JobDetail?jobId=15377&source=1111&tags=domestic+campus+2025_1111

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