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!!!Senior Signal and Power Integrity Engineer
面試心得
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企業名
聯發科技股份有限公司
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工作地點
新竹市東區
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薪資
面議(經常性薪資達4萬元或以上)40000~40000元
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工作內容
We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs.
1. Guide customers to complete Signal Integrity and Power Integrity signoff.
2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools.
3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes
4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models.
5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.
聯發科技股份有限公司-使用1111轉職專區
https://central1111.com.tw/turn/