轉職找工作推薦

應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • 電源管理晶片數位IC設計工程師 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 1. 電源管理晶片架構與系統設計(手機/車用) 2. 低功耗設計技術開發 3. 混合訊號數位 IP 設計: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs 4. 電源管理晶片整合: front-end and back-end integration
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

登入 後即可查看

根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

應徵
工作適配度－%

登入 後即可查看

根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • DFT/MBIST engineer for advanced process node & package technology 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • Senior DV engineer (micro-processor) 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 • Work with the architecture/micro-architecture/design teams to do white box testing. • Create testplans based on the micro-architecture document with the design team. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Build custom BFMs for co-sim based module level verification. • Add assertions and checkers to facilitate verification. • Work with the design team to do module level formal verification. • Create controlled random testcases. Pre-debug and provide debug reports. • Check functional coverage and code coverage.
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • Senior DV manager 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 • Lead the DV effort of a high-end CPU project. • Manage, coach and guide DV engineers. Follow up status and keep up the schedule. • Architect and implement top-module testbenches and their components using UVM-based methods. • Lead the effort of building in-house BFMs to facilitate co-sim based module level verification. • Architect and implement formal verification based module level testbench. • Work with the design team to create testplans. Implement checkers/assertions/coverage check points. • Work with validation folks to improve design visibility
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • Senior CPU Performance Modeling Engineer 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 • Work with the architecture team in the early stage of the project to derive various architecture and micro-architecture proposals. • Work with the performance architect to create performance models for various functional blocks of a microprocessor, memory subsystem and the whole core. • Work with design teams to analyze performance corner cases and provide feedback to the architecture team.
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

  • Analog/Mixed-Signal Modeling Methodology Development Engineer 面試心得
  • 企業名 聯發科技股份有限公司
  • 工作地點 新竹市東區
  • 薪資 面議（經常性薪資達4萬元或以上）40000~40000元
  • 工作內容 Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
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    • 聯發科技股份有限公司-使用1111轉職專區 https://central1111.com.tw/turn/
應徵
工作適配度－%

登入 後即可查看

根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

11/7

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