台灣高薪100轉職工作機會，轉職跳槽推薦工作，提供履歷健診等強化服務|1111轉職專區-第9頁

【2024 Campus Recruitment】TSMC Technician 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4300&source=1111&tags=2024DomesticCampus_1111 Description: 您可以根據所希望的工作地點和職務，投遞您的履歷到我們官網的以下職位： 1. 實驗室技術員 2. 龍潭先進封裝製造部技術員 3. 龍潭先進封裝工程部技術員 4. 竹科電子束作業處技術員 5. 竹科物流運籌系統部技術員 6. 竹南先進封裝製造部技術員 7. 竹南先進封裝工程部技術員 8. 中科技術員 9. 南科電子束作業處技術員 10. 南科物流運籌系統部技術員 11. 高雄製造部技術員(12吋廠) 12. 高雄工程部技術員(12吋廠) Qualifications: 1. 高中(職)以上畢業，不限科系 2. 細心、團隊溝通能力、自我學習能力、邏輯思考能力 3. 基本英文能力(機台介面)、Office 基本操作 4. 無經驗可，有相關經驗者尤佳

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC R&D Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4274&source=1111&tags=2024DomesticCampus_1111 Description: R&D Engineers will be part of a grand joint-force working on advanced technologies, including but not limited to exploratory research in advanced device architecture, market-oriented design IP enablement, device and process integration for manufacturability, package-level interconnect solutions, and novel material/equipment/process evaluations. 1. Research & Pathfinding (1) New material and new process pathfinding to enable new device architecture with integration (2) New tool pathfinding for new materials to enable the next nodes (3) Design, execute and analyze experiments to meet R&D engineering specifications (4) Process stability & manufacturability improvement for yield and reliability qualification (5) Process/tool transfer to development R&D or volume manufacturing (Fab) (6) Highly motivated individuals with a strong technical background and teamwork skills 2. Integration (1) Technology definition: design rules, design-technology co-optimization, logic/memory IP evaluations, etc. (2) Technology development infrastructure: productivity enhancement, product inspection methodology, mask-making, and test flow, etc. (3) New test vehicle establishment and validation: improvement of device yield and reliability (learning cycles). Improve yield and reduce defects by quantifying defect attributes using programming skills and developing effective detection methodologies. (4) Customer design enablement: SPICE Modeling and IP qualifications. 3. Module (1) Develop advanced processes, materials, tools, models, and computational methodologies for leading edge technologies. (2) Deliver manufacturable, stable, cost-effective technologies with device performance improvement for yield and reliability qualification. (3) Transfer process and tool to high volume manufacturing fab. 4. R&D Process Center (1) PE: Advanced module process development and baseline sustaining. (2) EE: Handle advanced equipment at R&D stage. Install, warm up, sustain and troubleshooting solve with new technology equipment. (3) MFG: Oversee the daily operations of IC foundry to ensure that all profiling operations, workflow, and customer reports are consistent with agreed upon service operations. Qualifications: 1. Passionate about the development of world-leading technologies. 2. Master‘s degree or above in an engineering or scientific field such as Materials Science Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 3. Solid technical understanding of IC processing equipment, integrated flow, chemistry, and physics. 4. Exhibit good and open communication skills and be able to work within cross-functional teams, including internal and external partners. 5. Fluent in English. 6. Skills in AI and programming are preferred. 7. Strong knowledge of Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles. Having knowledge of machine learning or artificial intelligence is an added advantage. 8. Flexibility in changing priorities and responsibilities to support business needs. 9. Hands-on participation on process or hardware and a strong sense of ownership. 10. Willing to make frequent fab presence. 11. Strong technical problem-solving and analytical skills, based upon fundamental, rather than empirical models is required. 12. Excellent written and spoken communication skills are required.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC DTP Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4275&source=1111&tags=2024DomesticCampus_1111 Description: At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. 【Physical Designer】 The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 【Standard Cell Engineer】 1. Pathfinding of library characterization for leading edge tech nodes 2. Support industrial standard library kits generation and QC 3. In-house library generation flow and/or utility development 4. RC parasitic extraction analysis and APR related analysis 【Layout Engineer】 1. IC layout for advanced technology (Std. cell/Memory/AMS/IO) 2. Layout structure development for new technology 3. Pathfinding for new technology development 4. Customer engagement and layout support 5. Design and technology co-optimization (DTCO) 6. AI and automation for layout and physical design 【System and Chip Design Solutions Development】 Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 【FE design & DFT】 1. Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG) 2. Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. 3. Technology benchmarking for PPA evaluation of the advanced nodes 4. DTCO (Design & Technology Co-Optimization) pathfinding and development 【SRAM Engineer】 1. SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. 2. RRAM/MRAM, emerging memory development 3. In memory computing research and development 【Design Flow/Methodology】 1. Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support 2. Advanced technology design development flow development and technical support 3. Automation program development to support design kits and flow development productivity/quality Qualifications: 1. Master‘s degree in Electrical Engineering or Computer Engineering 2. Strong proficiency in speaking and writing English 3. Thorough understanding of place and route flow 4. Excellent interpersonal and communication skills 5. Self-motivated and possess excellent team spirit

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC MtM RD Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4276&source=1111&tags=2024DomesticCampus_1111 Description: 1. Novel devices developing for specialty technology 2. Device Simulation, Test-chip design tape out and measurement system developing 3. Process flow developing for production 4. Collaborate with related teams for Design Collaterals (DRM/DRC/LVS/SPICE/PDK) developing Qualifications: 1. Master‘s degree or above in an engineering or scientific field such as Materials Science, Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 2. Experienced in process integration or HV/BCD devices developing and characterization. 3. Innovative problem-solving skills 4. Familiar with TCAD simulation is a bonus 5. Process integration & CMOS characterization 6. Solid technical understanding of IC processing equipment, integrated flow, chemistry, and physics. 7. Excellent communication skills and the ability to work within cross-functional teams, including internal and external partners.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC IIP Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4277&source=1111&tags=2024DomesticCampus_1111 Description: As a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer‘s variety applications. Integration: 1. Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline. 2. Package level reliability, failure mode analysis and improvement plan. 3. Customer technical interface, new tape out and lot handle. 4. Handover developed technologies to manufacturing groups for production. Module Development: 1. Be responsible for CVD / PVD / CMP / Lithography / Etch / Polymer / Bonding / Clean module development for 3DIC projects. 2. New technology, materials survey, and process improvement on 3DIC package structures. 3. Process development and tool transfer to mass-production development. Simulation: 1. Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment. 2. Practice FEM and DOE in problem solving and path finding particularly on packaging. 3. Continue improvement in simulation methodology, material modeling and script automation. Qualifications: 1. Master‘s degree or above in Chemical Engineering, Material Science, Chemistry, Physics, Mechanical Engineering, or related field in science or engineering 2. Experience in TV design or IC packaging is a plus 3. Good communication skills in Chinese and English 4. Hands-on participation and a strong sense of ownership are required 5. Strong technical problem-solving and analytical skills 6. For simulation positions, mastery of FEM software such as Ansys, LS-DYNA, Abaqus and others

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC R&D Pathfinding for System Integration Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4278&source=1111&tags=2024DomesticCampus_1111 Description: 1. Highly motivated veteran and new talents to join force research and pathfinding in Advanced packaging and system integration technologies for both extending Moore‘s Law and in post-Moore era. 2. Long prospective career path in semiconductor technologies looking at more Moore‘s and beyond Moore‘s Law Eco-industry. Job Description: 1. Integration engineering for process integration and device/system level modeling, including electrical, thermal, and mechanical modeling. 2. Module engineering in advanced FEOL/MEOL/BEOL wafer process modules, and in advanced system packaging, including wafer level fan-out, interposers, and 3D chip stacking 3. Silicon photonics expertise in the following areas: optical components design (lens, modulator, detector, waveguide w/ various materials), photonic circuits design (w/ focus on optical communication), and computer system architect with focus on parallel processing and high-speed networking. Qualifications: 1. Solid skills build-up with hands-on operation. 2. Positions are reserved for those who have strong interest in emerging, exciting and disruptive technologies and for those who enjoys an intellectual-stimulating environment with work-life balance. Engineers and scientists from well-experienced to new in system integration and relevant fields are encouraged to apply. 3. Master’s degree or above in Science/Engineering related field with strong motivation to grow in new field 4. Senior position in system-level pathfinding, innovative heterogeneous system integration, and technology road-mapping 5. Project/team management experience for management position.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC Process Integration Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4279&source=1111&tags=2024DomesticCampus_1111 Description: 1. A highly motivated individuals with a strong technical background and capabilities to develop and sustain process technologies for logic, flash memory, and specialty products. 2. Working with a team which may include device, integration, yield, lithography, etch and thin films or external suppliers to drive leading-edge integrated module development, control and improvements. 3. Be responsible for sustaining ownership such as day-to-day operations, equipment troubleshooting and mentoring technicians. 我們確保晶片的品質、持續提升良率，提供給客戶具有競爭力且高品質的晶片，讓電子產品不但先進且效能穩定；製程整合工程師為半導體製造中的重要協調者，需要與客戶溝通了解客製化的晶片應用需求，再將訊息帶回廠內，與各工程單位合作。良率精進工程師監控晶片的良率與缺陷，使用量測機台監測晶片的缺陷，找出可能的問題，再與製程解決問題。 Qualifications: 1. Master‘s degree or above in engineering or scientific field such as Materials Science, Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 2. Solid technical understanding of IC processing equipment, integrated flow, chemistry and physics. 3. Exhibit good and open communication skills, be able to work within cross-functional teams, including internal and external partners. 4. Fluent in English. 5. Strong knowledge of Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles. 6. Flexibility in changing priorities and responsibilities to support business needs. 7. Hands-on participation and a strong sense of ownership. 8. Willingness to make frequent fab presence. 在這個領域發光發熱，要具備：半導體元件物理與電性知識、英文與溝通能力、領導與問題解決能力、程式語言作為良率改善工具。

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC Process Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4280&source=1111&tags=2024DomesticCampus_1111 Description: 1. To be responsible to drive leading edge process/device/advanced packaging development and optimization of CMOS/Flash/Specialty devices in order to meet scaling, performance, reliability, and manufacturability requirements. 2. Identify and solve IC process and device problems. 我們在第一線負責晶片製造過程，改善機台製程參數的設定，提升良率並讓機台每單位時間產出增加，也降低生產成本；半導體製程可大致分為四大模組，大致流程順序為薄膜沈積、黃光微影製程、溼式與乾式蝕刻、熱製程與離子摻雜(擴散)。 Qualifications: 1. Master‘s degree or above in Electrical Engineering, Physics, Materials science, Chemistry or Chemical Engineering. 2. Semiconductor internship experience is preferred. 3. Exhibit good and open communication skills, be able to work within cross-functional teams. 4. Fluent in English. 在這個領域發光發熱，要具備：材料、物理、化學、機械背景知識、團隊合作、邏輯思考、問題解決能力

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC Equipment Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4281&source=1111&tags=2024DomesticCampus_1111 Description: 1. Master Nano Diffusion, Thin Film, Lithography, Etching, or Metrology equipment 2. Sustain and troubleshoot issues with high-tech equipment 3. Improve and enhance the efficiency and productivity of equipment 4. Plan and execute the analysis or defect detection projects 5. Communicate with cross-functional engineers or vendors 機台是工廠穩定運作的基礎，我們在生產線上，負責高端精密、高單價半導體設備的維護、保養並判斷、解決機台發生的問題；如此可減少機台當機的時間與提升機台可運轉的時間，進而降低生產成本並提升公司的獲利能力。 Qualifications: 1. Bachelor‘s degree or above in Electronics, Electrical Engineering, Mechanical and Automation Engineering related fields 2. No experience required. However, experience in equipment maintenance or improvement is a plus. 3. Have basic mechanical-related knowledge. Having the semiconductor processes knowledge is a plus 4. Good problem-solving skills, communication ability, team spirit, active learning attitude and is fluent in English 在這個領域發光發熱，要具備：電機、電子、機械與自動化工程等知識，還需要有良好的溝通能力、團隊合作精神、創新的問題解決能力

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

【2024 Campus Recruitment】TSMC Facility Engineer 面試心得
企業名台灣積體電路製造股份有限公司(台積電)
工作地點新竹縣寶山鄉
薪資月薪32000~43000元
工作內容【本職缺僅接受台積電官方網站投遞】請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4283&source=1111&tags=2024DomesticCampus_1111 Description: 1. Responsible for the planning, constructing, operating, and maintaining semiconductor plant facility systems, including risk analysis of facility system operations and supply quality, allocating resources and energy, managing construction safety. 2. Collaborate with other departments to ensure that the facility system is operating at the highest level of quality when on duty. 3. Provide a stable facility system to meet wafer production requirements. 4. Construction management & project coordination. Qualifications: 1. Bachelor‘s degree or above in Engineering, Materials Science, Environmental Engineering or related fields. 2. Strong communication and problem-solving skill with logical thinking and enjoy supporting the production related activities. 3. Ability to work independently and as part of a team. 4. Good work ethic and integrity, constantly innovating in daily operations.

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工作適配度－%

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根據履歷表的填寫狀況，智慧分析您與工作的適配程度。

5/10

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